Evolution of Green Industrial Growth between Europe and China based on the Energy Consumption Model

Greenhouse gas (GHG) emissions are an important factor in the evaluation of green industrial growth, when low GHG emissions along with high industrial growth are expected. In this paper, the improvement of sustainable development of industry in China (2007–2015) was investigated via analysis of the relationships between the GHG emissions and energy consumption in comparison to European countries. A hierarchical cluster analysis (HCA) was conducted to distinguish industrial growth with GHG emission and energy consumption structures. The results of this research indicated that green industrial growth in Europe had a negative annual rate of GHG emissions. This contributed to the ratio of renewable energy consumption increasing to a maximum of 33% and an average of 16%. In comparison, the GHG emissions in China increased at a rate of 50% to 77% in the main industrial provinces since 2007 with their rapid industrial growth. The rate of GHG emissions decreased after 2012, which was 7% or less than the rate of emissions in the industrial provinces. Contrary to in Europe, the decreasing rate of GHG emissions in China was attributed to the improvement of fossil energy efficiency, as renewable energy consumption was less than 10% in most industrial provinces. Our data analysis identified that the two different energy consumption strategies improved green industrial growth in Europe and China, respectively. Our data analysis identified the two different energy consumption strategies employed by Europe and China, each of which promoted green industrial growth in the corresponding areas. We concluded that China achieved green industrial growth through an increase in energy efficiency through technology updates to decrease GHG emissions, which we call the “China Model.” The “Europe Model” proved to be quite different, having the core characteristic of increasing renewable energy use

A New High Holding Voltage Dual-Direction Scr With Optimized Segmented Topology

While silicon controlled rectifiers (SCRs) are highly robust electrostatic discharge (ESD) protection devices, they typically are not suited for high-voltage ESD protection due to their inherently low holding voltage and thus vulnerability to latch-up threat. In this letter, a new high holding voltage dual-direction SCR (NHHVDDSCR) with a small area and optimized topology is developed in a 0.18-μm CMOS technology. The results of the NHHVDDSCR and other SCR devices measured from the transmission line pulsing are compared and discussed. It is shown that the NHHVDDSCR can possess a relatively high and adjustable holding voltage, as well as an acceptable failure current for robust ESD protection of high voltage applications

A Novel Dtscr With A Variation Lateral Base Doping Structure To Improve Turn-On Speed For Esd Protection

The turn-on speed of electrostatic discharge (ESD) protection devices is very important for the protection of the ultrathin gate oxide. A double trigger silicon controlled rectifier device (DTSCR) can be used effectively for ESD protection because it can turn on relatively quickly. The turn-on process of the DTSCR is first studied, and a formula for calculating the turn-on time of the DTSCR is derived. It is found that the turn-on time of the DTSCR is determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors. Using the variation lateral base doping (VLBD) structure can reduce the base transit time, and a novel DTSCR device with a VLBD structure (VLBD-DTSCR) is proposed for ESD protection applications. The static-state and turn-on characteristics of the VLBD-DTSCR device are simulated. The simulation results show that the VLBD structure can introduce a built-in electric field in the base region of the parasitic n-p-n and p-n-p bipolar transistors to accelerate the transport of free-carriers through the base region. In the same process and layout area, the turn-on time of the VLBD-DTSCR device is at least 27% less than that of the DTSCR device with the traditional uniform base doping under the same value of the trigger current. © 2014 Chinese Institute of Electronics

Evolution of the Individual Attitude in the Risk Decision of Waste Incinerator Construction: Cellular Automaton Model

In current work, the phenomenon of NIMBY (not in my back yard) for a municipal solid waste incinerator was recognized through an investigation for the evolution of individual risk attitude to group risk attitude (ItGRA). The cellular automaton model was employed to evaluate the risk attitude status with different frequencies of social interaction between residents. In the simulation case, the risk attitude of residents in the pseudo-rational state and non-pseudo-rational state was evaluated, which indicates the sheep-flock effect on the exaggeration of public NIMBY attitude. To the incinerator, the individual risk attitude evolved to supportive group risk attitude at a social interaction frequency 100 times higher than that in family or local neighborhoods, when the initial number of residents in opposition and support was equal. This was supported by the result of the model in the evaluation of resident risk attitude around the incinerator in Shanghai. On the contrary, for those in a non-pseudo-rational state, the ultimate group risk attitude depends on the probability that the residents have a supportive or opposing risk attitude as the concept of individuals was difficult to change. Accordingly, the decision strategy of incinerator construction should consider the influence of the sheep-flock effect, which can increase the attitude of residents in support and lead to the evolution of a group risk attitude to support attitude. Therefore, this study provides insight into the evolution of public attitude to NIMBY attitude and a promising evaluation method to quantify and guide the individual and group risk attitudes

A Reliability-Boosted Ferroelectric Random Access Memory With Random-Dynamic Reference Cells

Generating reference signal is indispensable and challenging in ferroelectric random access memory using one-transistor and one-capacitor architecture. This work presents an architecture with random-dynamic reference scheme for high speed and high reliability application. The detailed scheme and operating principle are illustrated. By rewriting memory cells and reference cells simultaneously after read process, the cycle time can be reduced. The data rewritten into reference cells are related to the data in memory cells, which can realize rewriting randomly 0 or 1 into reference cells. This method can balance the switch times of the pair of reference capacitors and restrain the floating of reference voltage generated for data read process, resulting in boosted reliability in the proposed architecture. A prototype based on the proposed architecture is fabricated and verified. It is exhibited that the proposed method can effectively reduce the cycle time and improve the operating speed. © 2014 IEEE

Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width

Reference Voltage Generation Scheme Enhancing Speed And Reliability For 1T1C-Type Fram

An improved reference voltage generation scheme is proposed for a 1T1C-type ferroelectric random access memory (FRAM), in which the circuit referring to reference cells is redefined and the data are written into reference cells at random between \u271\u27 and \u270\u27 depending on the voltages of the bitlines during every operation cycle. Compared with conventional schemes, it can not only realise higher access speed for memory, but also can enhance its reliability by resolving the imprint and relieving the fatigue relating to ferroelectric capacitors in the device. Functional verification for the experimental prototype utilising the proposed scheme has been implemented. © 2014 The Institution of Engineering and Technology

High-Speed And Low-Power Fram With A Bitline-Segmental Array

A bitline-segmental array architecture for ferroelectric random access memory (FRAM) is proposed to achieve lower power consumption and higher operation speed, in which the cell array is divided into four local blocks. Compared to the conventional array, the bitline-segmental arrays can decrease the power consumption by about 53 percent and 55 percent for read and write operation respectively. An experimental prototype utilizing the proposed architecture is implemented in 0.35 μ m 3-metal process and functionally verified